Internship, Process Engineer, Lithography, Terafab… at Tesla · Austin

Consider before submitting an application:

This position is expected to start around January 2027 and continue through the entire Spring term (ending approximately May 2027 or later, if available). We ask for a minimum of 12 weeks, full-time (40 hours/week) and on-site, for most internships. Our internship program is for students who are actively enrolled in an academic program. Recent graduates seeking employment after graduation and not returning to school should apply for full-time positions, not internships.

International Students: If your work authorization is through CPT, please consult your school on your ability to work 40 hours per week before applying. You must be able to work 40 hours per week on-site. Many students will be limited to part-time during the academic year.

Internship Program

The Internship Recruiting Team is driven by the passion to recognize and develop emerging talent. Our year-round program places the best students in positions where they will grow technically, professionally, and personally through their experience working closely with their Manager, Mentor, and team.

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

Process engineering is where Terafab technology gets built, atom by atom, and lithography will define the limit of what we can build. You will develop and own patterning processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory. With mask production in-house, you'll have unprecedented feedback loops to co-optimize reticle and scanner strategies.

Responsibilities

• Support process qualification for EUV and ArFi resist processes, exposure parameters, and coat/develop recipes

• Qualify scanners (EUV and DUV) from installation through production readiness, including dose-focus matrices, CDU, and overlay

• Support overlay and registration control strategies, scanner-to-scanner matching, and APC loop integration

• Analyze processes from a first-principles, physics-based approach to understand and manipulate mechanisms, not just recipes

• Assist root cause analysis, establish inline metrology and SPC control strategies, and drive systematic yield improvement

• Support next-generation lithography materials and process development

Requirements

• Currently pursuing a degree in Chemical Engineering, Materials Science, Electrical Engineering, Physics, or related field

• Familiarity with lithography process engineering in a semiconductor fab

• Ability to work closely and proactively across lithography, etch, thin films, integration, and equipment engineering teams

Compensation and benefits