DDR I/O Analog and Mixed-Signal Design… at Synopsys Inc · Yerevan

Descriptions & Requirements

Job Description and Requirements

Introduction:

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience:

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement:

Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

The Team You’ll Be A Part Of

You’ll join a team focused on DDR/LPDDR PHY and high-speed I/O circuit design, working alongside experienced analog and mixed-signal circuit designers. You’ll gain hands-on exposure to production-level PHY development, advanced semiconductor technologies, and modern IC design methodologies while receiving mentorship from experienced engineers.

What You’ll Be Doing

• Assist with transistor-level design and simulation of DDR I/O circuits.
• Analyze timing, power, signal integrity, and PVT variations.
• Contribute to the design and functional verification of TX, RX, clocking, calibration, and power-delivery circuits.
• Develop simulation testbenches and automate result analysis.
• Debug schematic, layout, and post-layout simulation results.
• Document technical findings and present results to the design team.
• Gain hands-on experience with production DDR/LPDDR PHY development and advanced semiconductor design methodologies.

The Impact You Will Have

• Contribute to the development and characterization of high-performance DDR/LPDDR PHY circuits.
• Support analysis and verification activities that help ensure circuit performance across different operating conditions.
• Help improve simulation and analysis efficiency through testbench development and automation.
• Contribute to identifying and resolving circuit-level issues through schematic, layout, and post-layout analysis.
• Build practical analog and mixed-signal IC design experience while contributing to real-world semiconductor development.

What You’ll Need

• Currently pursuing a BS or MS in Electrical Engineering or a related discipline.
• Coursework in analog/mixed-signal IC design, CMOS circuits, or VLSI.
• Understanding of MOS device operation and basic circuit analysis.
• Familiarity with SPICE simulation.
• Scripting experience with Python, Perl, Tcl, or Shell.
• Strong analytical, debugging, and communication skills.
• Knowledge of DDR, LPDDR, or other high-speed interfaces is a plus.
• Experience with Cadence or Synopsys custom-design tools is a plus.
• Familiarity with signal integrity, clocking circuits, statistical analysis, or post-layout verification is a plus.
• Exposure to advanced-node CMOS design is a plus.
• Good written and spoken English skills, including the ability to read and write technical documentation

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.