Senior Hardware Engineer-Platforms at Ross Video in Nepean, ON, Canada

Join the Hyperconverged Solutions R&D team developing the FPGA, SoC, embedded-control, and high-speed hardware platforms that power professional live video production.

This is a hands-on, on-site engineering role focused on system-level signal integrity, FPGA and SerDes bring-up, and practical hardware problem-solving. You will work directly with prototype hardware, lab equipment, FPGA tools, embedded software, PCB designers, and cross-functional engineering teams to bring complex products from architecture through production.

The ideal candidate is a pragmatic hardware systems engineer who understands how FPGA logic, PCB construction, signal integrity, power distribution, clocks, firmware, thermal behavior, and manufacturing interact. This position is expected to be primarily performed from the office and is not designed as a mostly work-from-home role.

What You Will Do

• Own or contribute to the architecture, design, implementation, bring-up, and sustaining support of FPGA-based hardware platforms.
• Develop and review requirements, component selections, schematics, FPGA partitioning, interface definitions, timing budgets, and technical risk assessments.
• Own or contribute to system-level signal-integrity analysis across the complete channel, including FPGA transceiver, package and pin breakout, connector, PCB, backplane, cable, and receiving device.
• Develop and review channel models, stackups, routing constraints, loss budgets, crosstalk assumptions, timing margins, and SI simulation results using HyperLynx or equivalent tools.
• Design and debug FPGA, SoC, CPLD, and embedded-control functions using SystemVerilog, Verilog, VHDL, C/C++, Python, Tcl, or shell scripting as appropriate.
• Work with PCB designers on high-density, high-speed boards, including component placement, transceiver breakouts, stackups, fabrication constraints, power distribution, thermal considerations, and design-for-manufacture.
• Bring up and validate high-speed SerDes links using oscilloscopes, BERT/JBERT equipment, vendor tools, eye diagrams, bathtub curves, BER testing, and structured margining.
• Configure and tune FPGA transceiver PMA and PCS parameters, including transmitter emphasis and equalization, receiver equalization, CTLE/DFE settings where applicable, output swing, polarity, clocking, reference clocks, lane alignment, and calibration behavior.
• Develop transceiver initialization, calibration, monitoring, and diagnostic flows that work across board revisions, temperature, voltage, manufacturing variation, and production units.
• Correlate simulation, FPGA transceiver settings, power behavior, and laboratory measurements to drive links to reliable operation.
• Determine whether failures originate in FPGA configuration, transceiver settings, reference clock, power integrity, PCB channel, connector, backplane, firmware, or the test setup.
• Write and debug low-level software, scripts, diagnostics, and register-access tools used for bring-up, testing, transceiver configuration, and production support.
• Support timing closure, CDC and reset analysis, implementation constraints, resource optimization, and FPGA debug.
• Participate in design reviews, validation planning, ECOs, board revisions, production transfer, RMA investigations, and field-return analysis.
• Collaborate with PCB, mechanical, software, verification, product validation, manufacturing, product management, and customer-support teams.
• Create clear architecture, design, bring-up, test, and troubleshooting documentation.
• Mentor less-experienced engineers and contribute reusable test methods, automation, diagnostics, and design practices.

Technical Environment

• Large routed platforms, processing blades, FPGA/SoC subsystems, I/O systems, PCIe and Ethernet backbones, crosspoint logic, and embedded control
• System-level SI and PI analysis, high-density PCB construction, stackup selection, high-speed routing, transceiver breakouts, timing budgets, and design-for-manufacture
• AMD and Intel FPGA/SoC devices, integrated transceivers, vendor IP, timing analysis, on-chip debug, PMA/PCS configuration, calibration, and margin testing
• SMPTE SDI, proprietary video interfaces, AES/MADI audio, Ethernet, PCIe, DDR3/DDR4/DDR5, source-synchronous buses, clocks, PLLs, and reset architectures
• Prototype bring-up, production readiness, manufacturing support, ECOs, board revisions, sustaining engineering, and field-return investigation

What We Are Looking For

Required Qualifications

• Several years of hands-on experience developing complex FPGA-based hardware or embedded hardware systems.
• Willingness and ability to work primarily from the office and spend substantial time in the lab.
• Demonstrated ability to physically debug hardware, including soldering, rework, probing, and using laboratory instrumentation.
• Strong system-level understanding of the interactions among FPGA logic, PCB design, power, clocks, resets, firmware, SI/PI, thermal behavior, and manufacturing constraints.
• Demonstrated experience with system-level signal integrity on high-speed digital hardware.
• Practical experience performing or interpreting SI simulations using HyperLynx or an equivalent tool.
• Practical experience with PCB stackups, high-speed channel construction, transceiver breakouts, connectors, backplanes, and loss/crosstalk tradeoffs.
• Hands-on experience bringing up and tuning FPGA or ASIC SerDes transceivers.
• Understanding of PMA/PCS architecture, transmitter and receiver equalization, calibration, reference clocks, lane alignment, initialization, eye measurements, and BER or margin testing.
• Experience with SystemVerilog, Verilog, or VHDL.
• Experience with schematic capture and PCB design-review processes.
• Experience with high-speed interfaces such as SDI, Ethernet, PCIe, serial transceivers, DDR, or comparable technologies.
• Experience diagnosing hardware failures through structured experiments, measurements, simulation, and root-cause analysis.
• Ability to communicate technical decisions clearly and work effectively across engineering disciplines.

Strongly Preferred

• AMD and/or Intel FPGA development experience, including timing closure, vendor IP, transceiver configuration, calibration, and on-chip debug.
• Experience with power-distribution networks, decoupling, power sequencing, monitoring, and power-integrity analysis.
• Embedded C/C++, Linux or RTOS-based systems, Python, Tcl, or shell scripting.
• Experience with PCIe-to-Ethernet architectures or low-level hardware-control software.
• Professional broadcast-video experience, particularly routing, distribution, multiviewer, or hyperconverged production systems.
• Experience using AI-assisted engineering tools with appropriate technical review and validation.

Working Style

We value engineers who are technically curious, direct, and practical. You should be comfortable making decisions with incomplete information, testing assumptions in the lab, and changing direction when the evidence says the original theory was wrong. The strongest candidates will be able to explain both the underlying electrical or FPGA principles and the practical steps they took to make a product work reliably.

What Success Looks Like

• High-speed links are brought up methodically and achieve reliable operation with documented margin.
• SI and PI risks are identified early and connected to practical design, layout, and validation decisions.
• Prototype and field failures are resolved through evidence-based root-cause analysis rather than speculation.
• Designs are practical, reviewable, testable, maintainable, and production-ready.
• Cross-functional teams receive useful technical direction, timely support, and clear documentation.
• The engineer becomes a trusted owner of significant subsystems and contributes to the reliability and maintainability of the overall platform.

Level and Growth

This is a Senior Engineer role with meaningful subsystem and platform responsibility. The successful candidate may grow into Principal-level scope by demonstrating sustained architectural ownership, technical leadership, cross-functional influence, and the ability to elevate the broader engineering team.