Senior Technical Architect at HCLTech in India

Job Summary

Own microarchitecture, RTL development and integration for PCIe, ASP and MMC subsystems.

Key Responsibilities

Develop synthesizable Verilog/SystemVerilog RTL.
Design/integrate PCIe, processor interfaces, DMA/GDMA, interrupts, NoC, telemetry and control logic.
Drive lint, CDC/RDC, synthesis, LEC and timing readiness.
Debug RTL/DV integration issues and support RTL Freeze/ECO closure.

Skill Requirements

Develop synthesizable Verilog/SystemVerilog RTL.
Design/integrate PCIe, processor interfaces, DMA/GDMA, interrupts, NoC, telemetry and control logic.
Drive lint, CDC/RDC, synthesis, LEC and timing readiness.
Debug RTL/DV integration issues and support RTL Freeze/ECO closure.