Power Engineer at Apple in Austin, TX

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Austin, Texas. Drive the budgeting, measurement, and analysis of overall CPU power. Work extensively with Micro-architects, RTL, physical designers, library and technology teams to study and drive power reduction opportunities. Collaborate closely with Micro-architect and RTL team to define traces and metrics of interest to track power for various use cases. Work with the design implementation team and optimize design operating points and power efficiency. Partner with CAD and driving tools and methodologies for power optimization. Collaborate closely with the SOC team to model and optimize CPU contribution of power. 40 hours/week.

Master’s degree or foreign equivalent in Electrical and Electronic Engineering or related field and 5 years of experience in the job offered or related occupation.
Experience and/or education must include:
Working with Synopsys© Prime Power for power analysis and optimization tasks.
Performing RTL-based power analysis to evaluate design power consumption.
Developing and managing CPU power budgets to ensure designs meet power targets.
Creating CPU power projections to forecast power consumption across different operating scenarios.
Analyzing and understanding CPU microarchitecture to inform design decisions and optimizations.
Writing scripts and developing programs to automate engineering workflows and analysis tasks.
Utilizing physical design flows and tools to analyze power consumption at gate level.
Utilizing power efficiency analysis for a project and comparison to all previous projects.
Working with physical design implementation team on pre-silicon dynamic and leakage power convergence including efficient clocking structures and power aware data path optimization

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