RTL Engineer – Physical AI Solutions

Location: San Jose, California, United States

Job Details:

Job Description:

Altera is empowering a new era of intelligent computing through programmable silicon solutions that accelerate innovation across cloud, edge, communications, industrial, automotive, and emerging AI applications. Our FPGA and adaptive computing technologies enable customers to build highly flexible, high-performance systems that can evolve with rapidly changing workloads.

We are seeking talented RTL Engineers to help develop next-generation hardware architectures that accelerate Physical AI workloads. This is an opportunity to work on cutting-edge FPGA and heterogeneous compute solutions that bridge the digital and physical worlds, enabling intelligent robotics, autonomous systems, machine vision, industrial automation, and real-time AI inference.

The Role

As an RTL Engineer, you will be responsible for designing, implementing, and verifying high-performance digital logic that powers AI and accelerated computing solutions. You will collaborate with architects, design verification engineers, software teams, and physical design engineers to deliver scalable and efficient hardware solutions targeting advanced FPGA and programmable logic platforms.

This role is ideal for engineers who are passionate about computer architecture, digital design, AI acceleration, and building hardware that enables real-world intelligent systems.

Responsibilities

• Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.

• Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.

• Create microarchitecture specifications and participate in architecture reviews.

• Optimize designs for performance, area, power, and scalability.

• Collaborate closely with design verification teams to define verification strategies and close functional coverage.

• Support FPGA implementation activities including synthesis, timing closure, and performance analysis.

• Work with firmware and software teams to enable hardware-software integration and system bring-up.

• Debug RTL, simulation, emulation, and silicon-related issues throughout the product lifecycle.

• Contribute to feature definition and architectural innovation for next-generation AI acceleration technologies.

• Participate in design reviews and maintain high standards for code quality and engineering excellence.

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149.1K - $238.2K USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.

• 3+ years of experience in RTL design and digital logic development.

• Strong expertise in Verilog and/or SystemVerilog.

• Solid understanding of computer architecture, digital design fundamentals, and ASIC/FPGA design methodologies.

• Experience with simulation, debugging, and verification tools.

• Experience developing high-performance datapath, control logic, or accelerator architectures.

• Familiarity with synthesis, static timing analysis, and FPGA implementation flows.

• Strong analytical, debugging, and problem-solving skills.

• Excellent communication and collaboration abilities.

Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.

• Experience designing AI, machine learning, vision-processing, signal-processing, networking, or robotics accelerators.

• Knowledge of FPGA architectures and adaptive computing platforms.

• Experience with industry-standard EDA tools such as Synopsys, Siemens EDA, or Cadence design environments.

• Understanding of high-bandwidth memory systems, NoC architectures, PCIe, Ethernet, CXL, or coherent interconnects.

• Experience with hardware/software co-design.

• Familiarity with Python, C/C++, or scripting languages used for design automation and validation.

• Experience developing solutions for robotics, industrial automation, autonomous systems, or edge AI applications.

What You'll Build

• FPGA-accelerated AI pipelines

• Real-time perception and sensor-processing systems

• Robotics and autonomous machine compute platforms

• Edge AI inferencing architectures

• High-performance programmable accelerator subsystems

• Next-generation adaptive computing solutions powering Physical AI applications

Why Join Altera?

• Shape the future of Physical AI and intelligent systems.

• Work on industry-leading programmable silicon technologies.

• Collaborate with world-class engineers solving complex hardware challenges.

• Influence next-generation computing architectures deployed across cloud, edge, and autonomous systems.

• Help bring AI closer to the real world through programmable, scalable hardware innovation.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.