AI Lead Architect - Silicon Design Execution at Altera… · San Jose

AI Lead Architect - Silicon Design Execution
Location: San Jose, California, United States
Job Details:
Job Description:
About Altera
Altera designs and delivers FPGA and adaptive computing solutions that help customers build differentiated, intelligent systems. This role is part of Altera's effort to modernize and accelerate its hardware design organization through the strategic application of AI.

Mission
Lead the AI transformation of hardware design across the organization.

Role Summary
Altera is seeking an AI Lead in HW Engineering to define and drive the company's AI strategy for chip design and to lead its deployment into design, verification, and implementation workflows. This is a senior, individual-contributor role intended for an engineer with deep hardware/EDA credibility who can act as a change agent — identifying where AI and machine learning can meaningfully accelerate and improve hardware development, building the case for adoption, and partnering with engineering teams across the organization to make it happen. The role carries no direct reports; impact comes through technical leadership, influence, and cross-team partnership rather than management authority.

Key Responsibilities
Define AI strategy: Develop and own a coherent strategy for how AI/ML is applied across hardware design, verification, and implementation, aligned to business priorities and engineering roadmaps.
Drive deployment, not just proof-of-concept: Lead the end-to-end path from identifying opportunities to piloting, validating, and deploying AI-driven tools and methods into production design, verification, and implementation flows.
Build and own the AI tooling stack: Specify, prototype, and productionize the tooling engineers actually use — retrieval over design collateral, specs, and historical debug data; agentic assistants for flow debug, script generation, and triage; and predictive models for quality-of-results and turnaround time — together with the evaluation harnesses that prove they work.
Own evaluation and operational discipline: Establish how AI tools are benchmarked, versioned, monitored, and retired, so adoption decisions rest on measured accuracy and engineer hours saved rather than demo quality.
Build the data foundation: Partner with CAD and IT to make design, verification, and signoff telemetry usable for ML — access, provenance, quality, and the IP-protection constraints that govern what can be used where.
Partner across the organization: Work directly with design, verification, DFT, implementation, and EDA tooling teams to understand workflow pain points and co-develop AI-based solutions that fit real engineering practice.
Act as a change agent: Build organizational buy-in for new AI-enabled workflows, addressing skepticism, workflow disruption, and adoption risk with credibility earned through hands-on hardware/EDA expertise.
Evaluate technology and vendors: Assess emerging AI/ML techniques, internal tooling, and third-party/EDA-vendor AI offerings for applicability to Altera's design flows, and make build-vs-buy recommendations.
Engage senior stakeholders and customers: Represent Altera's AI-in-design strategy and progress to senior internal stakeholders and, where relevant, customers and partners — building rapport and trust in technical conversations that carry real ambiguity and challenge.
Measure and communicate impact: Define success metrics for AI initiatives (e.g., turnaround-time reduction, quality-of-results improvement, engineer productivity) and report progress to leadership.
Mentor and uplift: Elevate AI/ML fluency across engineering teams through coaching, documentation, and hands-on collaboration, without formal management responsibility.

What Makes This Role Unique
This role sits at the intersection of AI leadership and deep hardware/EDA domain expertise — a combination that is rare and highly valued. The AI Lead is expected to function as a change agent within a large, complex engineering organization: someone who can move fluidly between design, verification, and implementation teams, translate between AI capability and hardware engineering reality, and build genuine partnership rather than impose top-down mandates. Success depends as much on relationship-building and influence as it does on technical depth.

Key Competencies
Technical credibility in hardware design and AI/ML — able to earn trust from engineering teams and speak authoritatively on both domains.
Influence without authority — able to drive change and adoption across teams without formal reporting lines.
Executive presence and diplomacy — comfortable navigating high-stakes, ambiguous, or contentious technical discussions with senior stakeholders and customers.
Strategic thinking — able to translate a broad AI opportunity space into a focused, prioritized roadmap.
Collaboration and partnership — builds genuine cross-functional relationships rather than working in isolation.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$206,400 - $303,250 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1
Qualifications:
Minimum Qualifications
12+ years of hands-on experience in semiconductor/hardware design, verification, or implementation, with deep familiarity with EDA tools and flows.
Demonstrated experience applying AI/ML techniques to real engineering workflows, ideally within chip design, verification, or physical implementation.
Working proficiency in Python and modern ML/LLM tooling, with hands-on experience in at least one of: LLM fine-tuning or post-training; retrieval-augmented generation over technical corpora; agentic frameworks and tool use; or classical ML applied to EDA data (ML-guided placement/routing, predictive timing/power, verification coverage optimization).
Track record of leading technical initiatives and driving adoption of new methodologies across engineering teams without direct management authority.
Demonstrated ability to engage senior customers, build rapport, and navigate challenging technical conversations with credibility, diplomacy, and influence.
Strong written and verbal communication skills, including the ability to present strategy and progress to senior leadership.
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Preferred Qualifications
Prior experience in an EDA company, semiconductor company, or FPGA/ASIC design environment.
Familiarity with machine learning frameworks and their application to EDA problems (e.g., ML-guided placement/routing, predictive timing/power analysis, verification coverage optimization).
Experience operating at a senior individual-contributor level (Principal/Distinguished Engineer or equivalent), influencing strategy and roadmap decisions.
Experience engaging directly with customers or external partners on technical strategy
Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.