STA Synthesis Engineer at Vhunt4u in Bengaluru, Malaysia

Sta Synthesis Engineer ( Visa Sponsored)

• Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions.
• Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics.
• Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
• Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints.
• Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase.
• Identify and resolve timing violations and sign-off on the final timing closure.
• Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy
• Key Skills-Static Timing Analysis, STA, Timing Analysis, Synthesis
• Mandatory skills -Static Timing Analysis, STA, Timing Analysis, Synthesis