ASIC Design Lead Level Professional at Tessolve · Hyderabad

Job Responsibilities
• Microarchitecture, Module design and simulation
• Digital design, implementation and integration RTL Coding, Lint, CDC, and Synthesis.
• Develop design constraints and coordinate to debug both functional and DFT test issues.
• Synthesis and P&R constraint generation, including clock tree specification
• Scan insertion and pattern generation
• Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.

Job Requirements
• BS/BEng in Electrical or Electronic engineering, MS preferred
• 8-12 yearsindustry experience with BS working in digital or mixed signal IC design
• Digital design knowledge:
• Verilog coding
• Register file design
• Serial interfaces
• Interconnect fabrics
• State machine architecture
• Clock domain crossing
• Scan and self-test
• Synthesis, Linting, STA
• Automation scripting and design flows
• Verification, including System Verilog knowledge
• Low power design, Power intent specification and validation methodology.
• System knowledge:
• Battery management and RISC-V based Subsystems/SOCs.
• Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.
• Familiarity with Cadence, Synopsis design tools
• Ability to work as part of a team and with low levels of supervision