Job Locations US-CA-Palo Alto

ID 2026-32824

We are seeking a highly skilled and motivated Power Integrity & Power Architecture
Engineer to lead the end-to-end design, modeling, simulation, and post-silicon
validation of advanced SoC power delivery architectures. In this role, you will bridge the
gap between System-on-Chip (SoC) design, power architecture, silicon packaging, and
system-level power integrity

Power delivery architecture, Design & Simulation
● Power Delivery Network (PDN) & Architecture: Define and optimize overall
SoC power architecture, establishing target impedance, transient droop
specifications, and efficiency targets across the full path: SoC/Packaging/Board.
● Advanced Power Supplier Architecture: Define requirements and simulation
flows for next-generation power supplier architectures, such as IVRs, integrated
switching regulators. Co-optimize power delivery for high efficiency, low supply
ripple, tight transient droop targets, and strict thermal limits across the SoC,
package and system.
● SoC Integration: Perform co-design and co-optimization for silicon packaging,
interposers, embedded passives to ensure robust power integrity.
● Multi-Domain Modeling: Conduct pre- and post-layout power integrity (PI),
signal integrity (SI), and IR/droop simulations using industry-standard 2.5D/3D
field solvers and circuit simulators.
Power integrity Validation
● Post-Silicon Bring-up & Correlation: Lead post-silicon validation and silicon
power integrity measurements (micro-probing, high-frequency VNAs, transient
load steppers, real-time scope measurements for PDN noise) to correlate lab
data with pre-silicon simulation models.
● System & Platform Validation: Collaborate with hardware and SoC bring-up
teams to validate SoC platforms under real-world dynamic workloads, verifying
transient performance, decoupling strategies, and power delivery margins.
Methodology
● Automation & Flow Optimization: Work alongside CAD and tool teams to
automate power integrity analysis, extraction workflows, and simulation scripts
(Python, Tcl, SKILL).

● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer
Engineering, or a related field.
● Experience: Proven industry experience in Power Integrity (PI), Power
Architecture for SoCs and advanced 2.5D/3D/MCM packaging.
● SoC Packaging: Deep understanding of System-on-Chip (SoC) power
distribution, package stack-ups, bump/ball maps, and silicon-package
interactions.
● Simulation & Tool Expertise:
○ EM & Extraction: Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or
Keysight ADS.
○ Circuit & PDN Simulation: HSPICE, Spectre, ADS, or SIMPLIS/SIMetrix.
● Post-Silicon Validation Capabilities: Hands-on expertise with high-speed lab
equipment (VNAs, oscilloscopes, active probes, impedance analyzers, load
steppers) for physical power validation and PDN characterization.
● Fundamentals: Strong foundation in power architecture, electromagnetics,
transmission line theory, s-parameters, and power distribution network (PDN)
noise dynamics.
Preferred Skills:
● Automation & Scripting: Proficiency in Python, Tcl, Perl, or Cadence SKILL for
automating simulation and extraction pipelines.
● Behavioral Modeling: Experience with Verilog-A, AMS, or SystemC for
macro-level system power modeling.
● Interface Noise Co-Design: Familiarity with high-speed interfaces (e.g., PCIe,
DDR, UCIe, die-to-die interconnects) and mitigating power supply switching
noise impacts on high-speed signals.

The salary range for this role is $237,200-$296,500 for Palo Alto, CA-based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors, including but not limited to specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for an annual performance bonus and equity awards.

We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits, including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.

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