CAD Infrastructure Intern at Rambus in San Jose, CA

Summary: Rambus is a premier chip and silicon IP provider seeking a CAD Engineering Intern to join their Central CAD Team. The intern will work on CAD tool, flow and methodology development, providing support for a global design team focused on advanced process technology nodes. Responsibilities: - Develop and support software utilities and automation, using Python, Tcl, Shell, or similar languages, to improve compute job throughput, turnaround time (TAT), and overall compute efficiency - Utilize the IBM LSF job scheduler to support and optimize job scheduling in on-premise data center and/or compute cloud environments - Work on electronic design automation (EDA) software license usage analysis and optimization, including improving license sharing efficiency and reducing tool contention in a shared global environment - Assist with monitoring, reporting, and analysis of infrastructure metrics, such as LSF job queue wait time, run time, resource utilization, and license consumption - Support LSF scheduler configurations and workflows to improve utilization of shared computing resources - Collaborate with CAD, IT, design, and verification teams to identify infrastructure bottlenecks and help develop scalable solutions - Support infrastructure used by chip design and verification workflows, including circuit simulation, logic synthesis, physical design, and design verification using EDA tools Required Qualifications: - Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field - Strong hands‑on software development and automation experience, with demonstrated ability to write high‑quality, well‑structured, and maintainable code, using Python (preferred) and/or Tcl, Shell, Perl, or similar languages - Familiarity with Linux/Unix environments - Basic understanding of semiconductor chip design and verification workflows, gained through coursework, academic projects, or internships - Exposure to electronic design automation (EDA) tools from software vendors such as Synopsys, Cadence, or Siemens, through academic or industry project work - Interest in compute infrastructure, job scheduling, or shared resource environments, including concepts such as throughput, turnaround time, and utilization - Strong analytical and problem‑solving skills, with the ability to learn new tools and technologies quickly - Good communication skills and ability to work effectively with CAD, IT, design, and verification engineers in a team environment Required Skills: Python, Tcl, Shell scripting, Perl, Linux/Unix, Semiconductor chip design, Chip verification workflows, Electronic design automation (EDA) tools, Job scheduling, Compute infrastructure, Analytical skills Benefits: Competitive compensation package including base salary, Bonus, Equity, Matching 401(k), Employee stock purchase plan, Comprehensive medical and dental benefits, Time-off program, Gym membership