NXP Semiconductors→

SoC Digital Physical Design Engineer - MCU at NXP… · Catania

ExperiencedOn-siteCatania, Sicily, IT

Skills

synopsys fusion compilersynopsys icc2synopsys primetimesynopsys design compilercadence innovuscadence tempuscadence genussiemens aprsiemens calibrefloorplanningpower planningplace and routeclock tree synthesisstatic timing analysisformal verificationphysical verificationdrclvsdfmtiming closurehierarchical staaocvpocvmulti-corner/multi-mode analysisir/em analysissignal integritytclpythonperlupfcpfclock gatingpower gatingmulti-vtproblem-solvinganalytical skillsdebugging skillscommunicationinterpersonal skillscollaborationtechnical leadershipmentoringadvanced tech nodes 16ff and below

Job Description

NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronicsNXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.This team will include all key engineering disciplines in Design, Architecture, Verification, DfT and Physical Design to produce high performance and quality products.We are now hiring a SoC Physical design leader responsible for the physical design implementation of complex, high-performance integrated circuits, from RTL to GDSII. The candidate will drive advanced methodologies, mentor and develop junior engineers, and contribute significantly to the successful tape-out of cutting-edge MCU SoC designs. Your Responsibility:

Lead projects and execute the full physical design flow for complex digital blocks and top-level SoCs, including floorplanning, power planning, synthesis, place and route, clock tree synthesis, static timing analysis (STA), formal verification, and physical verification (DRC/LVS).
Develop, optimize, and implement advanced physical design methodologies and flows to achieve aggressive performance, power, and area/cost targets.
Perform critical path analysis, identify timing bottlenecks, and implement effective solutions to meet timing closure on challenging designs operating at high frequencies.
Work closely with front-end design, architectural, and DFT teams to ensure design intent is preserved and to proactively resolve integration issues.
Drive power integrity (IR/EM) analysis and solutions, ensuring robust power delivery networks.
Conduct comprehensive physical verification checks (DRC, LVS, DFM) and resolve all issues efficiently.
Evaluate and recommend new EDA tools, technologies, and methodologies to enhance productivity and design quality.
Mentor and guide junior and mid-level physical design engineers, providing technical leadership and fostering a collaborative team environment.
Generate detailed technical documentation, reports, and presentations for design reviews and project milestones.
Contribute to the continuous improvement of design processes and best practices within the physical design team **Your Profile:**Master's degree in Electrical Engineering, Electronics Engineering, VLSI Design, or a related field.*Working knowledge on advance tech nodes 16ff and below is highly desirable. * Expert-level proficiency with industry-standard EDA tools from Synopsys (Fusion Compiler, ICC2, Primetime, Design Compiler), Cadence (Innovus, Tempus, Genus), or Siemens (APR, Calibre). * Deep understanding and practical experience with all aspects of the physical design flow, including floorplanning, power planning, block integration, P&R, CTS, STA, Formal Verification, and Physical Verification. * Strong expertise in timing closure, including hierarchical STA, AOCV/POCV, multi-corner/multi-mode analysis, and complex timing constraint debug. * Proven experience in power integrity analysis (IR/EM) and optimization techniques. * Solid understanding of signal integrity (SI) issues and solutions. * Proficiency in scripting languages such as Tcl, Python, and Perl for automation and flow development. * Familiarity with low-power design techniques (UPF/CPF, clock gating, power gating, multi-Vt). * Excellent problem-solving, analytical, and debugging skills. * Strong communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and mentor junior engineers. * Prior experience in a technical leadership role, driving projects and influencing technical direction.**Commitment At NXP.**We recognize we can be a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

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