Technical Program Manager – GPU Floorplanning at Nvidia · Santa…

Technical Program Manager – GPU Floorplanning Location: US, CA, Santa Clara Our technology has no boundaries! Nvidia is building the world’s most groundbreaking and state of the art compute platforms for the world to use. It’s because of our work that scientists, researchers and engineers can advance their ideas. At its core, our visual computing technology not only enables an amazing computing experience, but it is also energy efficient! We pioneered a supercharged form of computing loved by the most demanding computer users in the world - scientists, designers, artists, and gamers. It’s not just technology though! It is our people, some of the brightest in the world, and our diverse company culture make NVIDIA one of the most fun, innovative and dynamic places to work in the world! At the center of NVIDIA's culture are our core values like innovation, excellence and determination and team, that guide us to be the best we can be. NVIDIA is seeking a highly capable Technical Program Manager (TPM) to partner closely with our GPU Floorplan team and multi-functional collaborators in driving the execution of large, complex, multi‑die SoC and chiplet programs. This role sits at the intersection of deep technical understanding and disciplined program execution. The TPM will work alongside floorplan, chiplet, architecture, PD, package, and design teams to ensure coherent planning, clear prioritization, and predictable delivery across fast‑moving and highly interdependent programs. The ideal candidate brings strong program management rigor and enough technical depth to understand early‑phase physical design and system‑level trade‑offs, enabling them to ask the right questions, surface risks early, and help the team stay focused on the highest‑impact work. What you’ll be doing: Own and drive end‑to‑end execution tracking for large‑scale GPU / SoC floorplan programs across multiple dies and chiplets. Build and maintain integrated program views spanning breakthroughs, dependencies, risks, and cross‑team interactions. Ensure plans from multiple chiplet / die owners roll up into a cohesive, executable project‑level view. Partner closely with floorplan and technical leads to identify, track, and prioritize critical technical issues impacting area, wiring, timing, and schedule. Proactively identify execution risks, misalignment, and early warning signals across the program. Drive structured risk reviews and mitigation planning, ensuring issues are visible early rather than discovered late. Serve as a primary coordination point between floorplan and partner teams including architecture, RTL, PD, DFT, package, design, and tooling. Improve the quality, consistency, and predictability of interactions across teams. Help rationalize and mature program management processes as programs grow in size and complexity. Champion better tooling, dashboards, and structured ways of working that reduce overhead on technical leads. What we need to see: Bachelor’s degree in Electrical Engineering, Computer Engineering or equivalent experience. 10+ years of relevant working experience. Strong program or technical project management experience in complex hardware or silicon development programs. Proven ability to manage highly interdependent, multi‑threaded execution across multiple partners. Sufficient technical depth to understand and engage on topics such as SoC architecture, physical design flows, floorplanning, or chip integration (not hands‑on implementation, but informed judgment). Excellent written and verbal communication skills, with the ability to synthesize complexity into clear status and decisions. Ways to stand out from the crowd: Prior experience supporting floorplan, physical design, chip integration, or early silicon planning teams. Experience working on multi‑die, chiplet‑based, or large SoC programs. Ability to operate effectively in environments with incomplete data, evolving requirements, and tight milestones. Strong judgment in prioritization - knowing when to push, when to call out, and when to unblock quietly. NVIDIA offers highly competitive salaries and a comprehensive benefits package. We have some of the most forward-thinking and dedicated people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until May 3, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.