ASIC Clocks Design Engineer - New College Grad 2026 at Nvidia · Austin

ASIC Clocks Design Engineer - New College Grad 2026 Location: US, CA, Santa Clara NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. We are looking for an ASIC Clocks Design Engineer to join the team. Our team crafts all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab. What you'll be doing: As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements. Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking. Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup. What we need to see: Bachelor's degree or higher in Electrical Engineering (or equivalent experience). Understanding of logic optimization techniques and PPA trade-offs. Shown ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis. Strong coding skills in Python or other industry-standard scripting languages. Ways to stand out from the crowd: Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Implementing on-chip clocking networks is a bonus. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until June 7, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. Additional Locations: US, TX, Austin