NVIDIA AI→
ASIC Design Engineer - New College Grad 2026 at NVIDIA AI · Westford
Entry LevelOn-siteWestford, MA$100k–$167k/yr
Skills
verilogsystem veriloghigh speed designlow power design methodologieslogic designmicroarchitecture developmentrtl implementationsynthesistiming closurepowernoise analysishardware engineering support
Job Description
Summary: NVIDIA AI is dedicated to pioneering visual computing and AI technology. They are seeking an ASIC Design Engineer to engage in the design and development of NVIDIA’s next generation NVLink protocol, working collaboratively with a team to optimize performance and power goals.
Responsibilities:
- Engaging in and support the design and development of NVIDIA’s next generation NVLink protocol
- Participating in microarchitecture development and document specifications
- Implementing in RTL and debug working with the verification team to ensure that the design is functional and performant
- Applying logic design skills to optimize and meet performance and power goals
- Delivering a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design
- Supporting hardware engineering activities including chip floor plan, power/clock distribution, timing closure, power and noise analysis, and back-end verification
- Developing flows and tools as necessary in support of design activities
Required Qualifications:
- Bachelors Degree in EE, CS or CE (or equivalent experience)
- Strong working knowledge of Verilog or System Verilog
- Project and/or design experience with high speed (>1GHz) design
- Project and/or design experience with low power design methodologies
- Strong collaboration and communication skills
Preferred Qualifications:
- Internships and/or project experience with Verilog/system verilog
- Background with low power design methodologies
- Experience with high speed design methodologies
Required Skills: Verilog, System Verilog, High speed design, Low power design methodologies, Logic design, Microarchitecture development, RTL implementation, Synthesis, timing closure, Power, noise analysis, Hardware engineering support
Benefits: Equity, Benefits
Benefits
Equity
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