Digital Verification Engineering Intern at Impinj in Seattle, WA

Summary: Impinj is a leading RAIN RFID provider and Internet of Things pioneer. They are seeking a Digital Verification Intern to join their Digital Tag Design Team, where the intern will work closely with engineers to improve the digital tag verification environment. Responsibilities: - Expand the UVM/SystemVerilog functional coverage model in our digital simulation environment - Identify unit functional coverage points uncovered through simulation - Design tests which address these coverage gaps by exploring previously un-exercised behavior Required Qualifications: - Currently enrolled in a Bachelor's or Master's program in Electrical Engineering or a related field - 1-3+ years of relevant coursework experience - A strong desire to learn about RFID ASIC design, digital simulation environments, and digital RTL verification - Experience using at least one hardware description language (VHDL, Verilog, SystemVerilog) - Experience with at least one other programming language (C, C++, Python, Perl, Ruby, Java, etc.) - Strong communication and documentation skills Required Skills: UVM, SystemVerilog Important Skills: VHDL, Verilog, C++, Python Nice-to-Have Skills: Communication skills, Documentation skills Benefits: Healthcare benefits, 401(k) plan and company match, Merit increases, Annual bonus, Stock, Sales incentives based on revenue or utilization, Open paid time-off policy