Staff RTL IP/Component Design Engineer, Google… at Google · Tel Aviv

Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc. Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks. Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and SOC-level verification. Communicate and work with multi-disciplined and multi-site teams.