Senior CMOS Test and Validation Lead, Analog… at Google · Fremont

Lead and mentor a team of test and validation engineers through the entire post-silicon lifecycle, from first-silicon bench bring-up to ATE production release. Partner with IC Design and DFT teams during the pre-tapeout phase to define Post SIlicon Test Process and Design requirements. Design, develop, and debug multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) focusing on high-efficiency parallel testing for digital and AMS blocks. Drive exhaustive post-silicon validation across PVT corners. Ensure strict bench-to-ATE correlation for critical high-speed interfaces and analog blocks. Oversee the architecture and schematic review of complex loadboards and probe cards, ensuring Signal Integrity and Power Integrity (SI/PI) standards are met for high-frequency measurements. Automate data collection from wafer test.