Senior CAD Infra Engineer at Google in Tel Aviv, Tel Aviv, Israel

Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies. Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs. Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow. Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.