Chip Package Signal and Power Integrity Engineer at Google · Sunnyvale

Drive chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for HPC based on 2.5D/3D package technology. Develop Power integrity methodology for advanced package technology, and Methodology development to enhance accuracy and productivity. Evaluate New package technology and development, and High speed Interface IP. Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, define boundaries of chip design and explore SI/PI and DFM trad-eoff for package design closure for production. Provide feedback on chip floorplan considering package/system routability and SI/PI.