HW Design Verification Intern at d-Matrix in Santa Clara, CA

Summary: d-Matrix is focused on unleashing the potential of generative AI to power the transformation of technology. They are seeking an intern to work alongside a team building state-of-the-art LLM inference SoCs, contributing to functional verification and improving simulation efficiency. Responsibilities: - You’ll contribute to the functional verification of complex hardware blocks using UVM-based methodologies and - Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA) - You’ll also develop and maintain tools that improve simulation efficiency and verification productivity, and - Help explore how emerging AI-assisted workflows can strengthen DV methodology Required Qualifications: - Pursuing a Master's or PhD degree in Electrical and Computer Engineering, or a related scientific discipline - Relevant coursework in Computer Architecture, Verilog, and/or FPGA development - Familiarity with the SystemVerilog programming language - Excellent verbal and written communication skills Preferred Qualifications: - Familiarity with SystemVerilog Assertions (SVA) - Current knowledge of AI SoC and/or LLM inference architectures Required Skills: SystemVerilog, SystemVerilog Assertions, UVM-based methodologies, Functional verification, Formal verification techniques, Hardware design verification, Computer Architecture, Verilog, FPGA development, AI SoC architectures, LLM inference architectures