Fall 2026 Co-Op - Mixed Signal Modeling &… at Cirrus Logic · Austin

Summary: Cirrus Logic has been a leader in mixed-signal processing for over four decades, known for its innovative solutions and award-winning culture. They are seeking a creative and hardworking engineering intern to join their Analog/Mixed-Signal Verification, Modeling and Methodology Team, where the intern will collaborate with experienced engineers to develop and validate System Verilog models and perform AMS/UVM verification. Responsibilities: - You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs for audio processing applications - Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS - Independent Interpretation of analog circuit schematics into abstract models - Performing regression debug support and other flow/infrastructure development Required Qualifications: - Actively pursuing a Bachelors, Masters, or PhD in Electrical Engineering or Computer Engineering - Good understanding of analog integrated circuit design - Experience with System Verilog real number modeling (RNM) modeling and/or Verilog-A behavioral modeling - Organized and detailed with strong communication skills - Possess outstanding analytical and problem-solving skills - Results-oriented and ability to operate in dynamic environment Required Skills: Analog integrated circuit design, SystemVerilog real number modeling, Verilog-A behavioral modeling, Verification planning, AMS simulation, Behavioral modeling, Regression debug, Flow development, Infrastructure development, Analytical skills Internship Start Date: Start in 2026 Fall