Fall 2026 Co-Op - Design Verification… at Cirrus Logic · Austin

Summary: Cirrus Logic is a leader in mixed-signal processing, known for its award-winning culture and commitment to inclusion. They are seeking highly motivated interns to join their Mixed-Signal Verification Engineering team to support the functional verification of industry-leading mixed-signal products. Responsibilities: - Assist in verification planning and strategy development - Support testbench creation, maintenance, and enhancement - Contribute to failure analysis, debug, and resolution efforts - Help with coverage analysis and population to ensure thorough verification of mixed-signal products - Work on digital/mixed-signal modeling, directed and constraint-random test generation, and verification flow development Required Qualifications: - Currently pursuing a MS or PhD in Electrical Engineering or a related field - Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL - Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM, Vera, or e - Solid understanding of digital design fundamentals and verification methodologies Required Skills: Hardware Description Languages, Verilog, VHDL, Hardware Verification Languages, SystemVerilog, UVM, Vera, e, Digital Design Fundamentals, Verification Methodologies Internship Start Date: Start in 2026 Fall