Design Verification Engineer Intern at Cadence in San Jose, CA

Summary: Cadence is a leader in computational software and semiconductor design, seeking a Design Verification Engineer Intern to join their Silicon Realization Group in San Jose. The intern will work closely with verification engineers to verify digital designs and contribute to high-quality silicon delivery. Responsibilities: - Develop and maintain verification environments using SystemVerilog/UVM - Write and execute test cases to validate RTL functionality - Debug design and verification issues using simulation and waveform analysis - Collaborate with design teams to review specifications and verification plans Required Qualifications: - Currently pursuing a BS/MS in Electrical Engineering, Computer Engineering, or related field - Strong understanding of digital design fundamentals and RTL concepts - Working knowledge of Verilog/SystemVerilog - Familiarity with EDA simulation tools - Good analytical, communication, and teamwork skills Preferred Qualifications: - UVM is a plus - scripting (Python/Perl preferred) Required Skills: Digital Design Fundamentals, RTL Concepts, Verilog, SystemVerilog, UVM, EDA Simulation Tools, Python, Perl