Design Verification Engineer Intern at Cadence in SAN JOSE

Summary: Cadence is a world leader in computational software and semiconductor design. They are seeking a motivated Design Verification Engineer Intern to work closely with Verification engineers to verify digital designs for correctness and performance. Responsibilities: - Develop and maintain verification environments using SystemVerilog/UVM - Write and execute test cases to validate RTL functionality - Debug design and verification issues using simulation and waveform analysis - Collaborate with design teams to review specifications and verification plans Required Qualifications: - Currently pursuing a BS/MS in Electrical Engineering, Computer Engineering, or related field - Strong understanding of digital design fundamentals and RTL concepts - Working knowledge of Verilog/SystemVerilog - Familiarity with EDA simulation tools - Good analytical, communication, and teamwork skills Preferred Qualifications: - UVM is a plus - scripting (Python/Perl preferred) Required Skills: Digital Design Fundamentals, RTL Concepts, Verilog, SystemVerilog, UVM, EDA Simulation Tools, Python, Perl