System Validation Engineer (Intern 2026) at Astera Labs · San Jose

.Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Astera Labs is a rapidly growing semiconductor company that’s redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you’ll help validate the silicon that powers the world’s most advanced AI platforms. Role Overview As a Post-Silicon Validation Intern, you’ll work alongside seasoned engineers to validate high-speed interconnects and AI fabric technologies in Astera Labs’ custom silicon products. You’ll gain hands-on experience with PCIe Gen5/Gen6, CXL, and memory-semantic fabrics, contributing directly to the bring-up and debug of chips that enable hyperscale AI workloads. Key Responsibilities Execute post-silicon validation test plans for PCIe®, CXL™, and other high-speed interfaces Use lab equipment (oscilloscopes, protocol analyzers, BERTs) to validate signal integrity and protocol compliance Develop and debug test automation scripts in Python, C/C++, or TCL Analyze performance, latency, and error recovery across AI connectivity fabrics Collaborate with design, firmware, and systems teams to root-cause issues and optimize performance Document validation results and contribute to debug guides and bring-up documentation Required Qualifications Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field Solid understanding of digital logic, computer architecture, and high-speed serial protocols Familiarity with PCIe®, CXL™, or Ethernet standards Experience with scripting languages (Python, TCL) and basic programming (C/C++) and JMP Comfortable working with lab tools and debugging hardware Strong analytical and communication skills Preferred Skills Exposure to post-silicon validation or bring-up of connectivity IP blocks Knowledge of signal integrity analysis and eye diagram interpretation Familiarity with Linux systems, shell scripting, and version control (Git) Understanding of AI workloads and how interconnect bandwidth impacts performance Experience with memory coherency protocols and cache hierarchies What You’ll Gain Hands-on experience with industry-leading connectivity solutions for AI infrastructure Mentorship from engineers at the forefront of silicon innovation Exposure to the full lifecycle of chip development—from tape-out to deployment Opportunity to contribute to products used by top hyperscalers and cloud providers Potential pathway to a full-time role at Astera Labs We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.