Digital Design Engineer (Internship) at Astera Labs in San Jose, CA

Summary: Astera Labs is a company providing rack-scale AI infrastructure through innovative connectivity solutions. They are seeking a Digital Design Engineering Intern to join their ASIC team, focusing on design and verification of blocks in advanced CMOS process nodes. Responsibilities: - Design and/or verification of blocks using leading edge methodology and tools Required Qualifications: - Pursuing BS or MS in EE/CS or related fields - Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture - Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog - Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C Preferred Qualifications: - Real-world design and/or verification in Verilog/System Verilog - Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes - Familiarity with Synopsys EDA tools Required Skills: RTL design, Verilog, System Verilog Important Skills: Digital design, VLSI design, Computer Architecture, High-speed interfaces Nice-to-Have Skills: Python, Perl, C, Synopsys EDA tools