FPGA Digital Design and Verification… at Altera · San Jose

Summary: Altera is seeking a highly motivated FPGA Digital Design and Verification Engineer-Contract. The role involves collaborating with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products. Responsibilities: - RISC-V design - Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems - Create self-checking testbenches, constrained-random tests, and functional coverage models - Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness - Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim) - Assist in debugging RTL and verification failures, working closely with design engineers - Verify common communication protocols (e.g., UART, SPI) and custom interconnects - Contribute to documentation of verification plans, test strategies, and results - Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components Required Qualifications: - Bachelor's Degree in Computer or Electrical Engineering or related field - 1+ years' experience in Digital Logic Design and Computer Architecture - RISC-V and digital design experience - Proficiency in SystemVerilog and Verilog - Knowledge of UVM, functional coverage, constrained random verification, and assertions - Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS - Familiarity with Linux-based development environments - Ability to debug simulation issues and analyze waveforms effectively Preferred Qualifications: - Experience verifying communication protocols (UART, SPI, AXI preferred) - Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado - Knowledge of SVA or formal verification concepts - Programming or scripting experience in Python, Perl, Tcl, or C - Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads Required Skills: Digital Logic Design, Computer Architecture, RISC-V, SystemVerilog, Verilog, UVM, Functional Coverage, Constrained Random Verification, Assertions, Simulation Tools, ModelSim, QuestaSim, Synopsys VCS, Linux Development Environment, Debugging Simulation Issues, Communication Protocols, UART, SPI, AXI, FPGA Tools, Intel Quartus Prime, Xilinx Vivado, SVA, Formal Verification, Programming, Python, Perl, Tcl, C, SoC Design, Hardware Acceleration for AI/ML Benefits: Incentive opportunities that reward employees based on individual and company performance