Design Verification Engineer at Altera Corporation in San Jose, CA

Design Verification Engineer Location: San Jose, California, United States Job Details: Job Description: About the Role: Altera is a leading FPGA (Field-Programmable Gate Array) company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. With over four decades of experience in programmable logic, our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules—supported by industry-leading tools like the Quartus development suite. Recently re-established as an independent business (with Intel retaining a minority interest), Altera is focused on accelerating programmable compute in AI, networking, communications, industrial, automotive, aerospace/military, and edge-computing domains. Our mission is to provide leadership programmable solutions that are easy to design and deploy, and our vision is to pioneer innovation that unlocks extraordinary possibilities. We are seeking a Sr. Silicon Design Verification Engineer (on-site) who can perform the following functions: Performs functional logic verification at multiple levels ( block, subsystem and full chip ) Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $133,200 - $192,000 USD We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations. Qualifications: Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 6+ years of technical experience. Experience in Validation/Verification. Related technical experience should be in/with: Pre Silicon 6+ years of experience with OVM/UVM, System Verilog, constrained random verification methodologies. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.