Founding Engineer - Cluster/Hardware/Systems

Summary: Zettascale Computing Corp. is building the next generation of chips to power AI, and they are seeking a Founding Engineer to join their team. The role involves designing high-speed PCBs and systems-level hardware with a focus on AI compute engines and cluster architectures. Responsibilities: - Design high-speed PCBs for AI compute engines - Develop systems-level hardware architecture - Optimize dataflow for AI models - Collaborate with the founding team on critical decisions - Work across PCB, mechanical, thermal, and system architecture Required Qualifications: - Background in Electrical Engineering, Mechanical Engineering, Engineering Physics, or equivalent field - Strong high-speed PCB design experience (high layer count, controlled impedance, stackup design, via optimization) - Signal integrity & power integrity expertise (SI/PI simulation, eye diagrams, S-parameter analysis, decoupling strategy, IR drop) - High-speed interface design (PCIe Gen5/6, CXL, DDR5/HBM, Ethernet 400G/800G, SerDes routing) - Proficiency with PCB toolchains (Altium, Cadence Allegro, KiCad, HyperLynx, Ansys SIwave/HFSS) - Cluster & system-level design experience (server/blade architecture, backplanes, rack-scale interconnect topologies) - Thermal & cooling expertise (air, liquid, and immersion cooling; thermal simulation; cold plate design; airflow modeling) - Power delivery design (multi-phase VRMs, high-current PDN, board-level power sequencing) - Bring-up & debug expertise (oscilloscopes, VNAs, TDR, BERT, JTAG, root-causing SI/PI/thermal issues on real boards) - Build/flow automation and tooling (Python, Tcl, Nix) - Work across PCB, mechanical, thermal, and system architecture to hit cluster-level PPA targets Preferred Qualifications: - Experience designing AI/HPC accelerator boards or systems (GPU servers, TPU pods, custom ASIC carrier boards) - Rack-scale & data center experience (OCP designs, NVLink/NVSwitch-class fabrics, optical interconnects, top-of-rack networking) - Liquid/immersion cooling deployment experience (cold plate design, CDU integration, two-phase cooling, leak mitigation) - DFM/DFT-aware PCB design (manufacturability reviews, test point strategy, boundary scan, bed-of-nails) - Experience writing/maintaining reusable hardware IP (reference designs, modular board architectures, well-documented schematics) - 2-5+ years (or equivalent) designing high-speed, high-layer-count PCBs for ASICs, GPUs, or networking gear - Mechanical/enclosure design experience (sheet metal, chassis design, working with ME/Industrial Design teams) - HW/SW boundary experience (board bring-up, BMC/firmware, telemetry, profiling, build systems) - Experience with systems programming (Linux drivers, low-level board management) - Experience with (Sci)ML frameworks (e.g., PyTorch/TinyGrad/JAX/Lux.jl) - Autodidactic polymath with a strong mathematical background - Someone who doesn't fret when faced with near-impossible technical challenges Required Skills: High-speed PCB design, Signal integrity, Power integrity, SI/PI simulation, Eye diagram analysis, S-parameter analysis, Decoupling strategy, IR drop analysis, High-speed interface design, PCIe Gen5/6, CXL, DDR5, HBM, Ethernet 400G/800G, SerDes routing, PCB toolchains, Altium, Cadence Allegro, KiCad, HyperLynx, Ansys SIwave, Ansys HFSS, Cluster design, System-level design, Server architecture, Blade architecture, Backplanes, Rack-scale interconnect, Thermal expertise, Cooling expertise, Air cooling, Liquid cooling, Immersion cooling, Thermal simulation, Cold plate design, Airflow modeling, Power delivery design, Multi-phase VRMs, High-current PDN, Board-level power sequencing, Bring-up, debug, Oscilloscope use, VNA use, TDR, BERT, JTAG, SI/PI/thermal root cause analysis, Build automation, Flow automation, Python, Tcl, Nix, AI/HPC accelerator board design, GPU server design, TPU pod design, ASIC carrier board design, Rack-scale experience, Data center experience, OCP design, NVLink, NVSwitch, Optical interconnects, Top-of-rack networking, DFM-aware PCB design, DFT-aware PCB design, Manufacturability reviews, Test point strategy, Boundary scan, Bed-of-nails testing, Reusable hardware IP design, Mechanical design, Enclosure design, Sheet metal design, Chassis design, HW/SW boundary experience, Board bring-up, BMC firmware, Telemetry, Profiling, Build systems, Systems programming, Linux drivers, Low-level board management, Scientific machine learning frameworks, PyTorch, TinyGrad, JAX, Lux.jl, Passion for computing, AI, Technical obsession Benefits: Highly competitive compensation + significant equity