UIUC Research Park Intern - Functional Safety Hardware

Summary: Rivian is on a mission to keep the world adventurous forever, focusing on building emissions-free Electric Adventure Vehicles. They are seeking a detail-oriented Hardware Functional Safety Engineer Intern to support the functional safety lifecycle for hardware components through rigorous analysis and documentation. Responsibilities: - Your primary focus will be supporting the functional safety lifecycle for hardware components through quantitative and qualitative analysis - FTA (Fault Tree Analysis): Support top-down FTA to identify combinations of hardware failures that could lead to a violation of safety goals. You will help build logic trees to visualize and quantify the probability of catastrophic system failures - DFA (Dependent Failure Analysis): Conduct DFA to identify potential "freedom from interference" issues. You will analyze shared resources (e.g., clock trees, power rails, or physical proximity on a PCB) to identify Cascading Failures and Common Cause Failures (CCF) that could bypass safety redundancies - FMEDA (Failure Modes, Effects, and Diagnostic Analysis): Assist in performing quantitative FMEDA to calculate hardware architectural metrics (SPFM, LFM) and the Probabilistic Metric for random Hardware Failures (PMHF). You will evaluate the effectiveness of safety mechanisms in detecting or controlling hardware faults - Design Review: Review hardware requirements and schematics to ensure safety mechanisms (e.g., ECC, parity, redundant paths, voltage monitors) are correctly implemented to mitigate the faults identified in your FTA and DFA - Documentation: Contribute to the creation of Work Products required by ISO 26262, such as the Hardware Safety Analysis Report and Safety Case fragments Required Qualifications: - Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign - Actively pursuing a degree or one closely related in Electrical Engineering or Computer Engineering - Foundational knowledge of ISO 26262 (specifically Parts 5, 9, and 11) - Understanding of FTA (Qualitative/Quantitative) and the principles of DFA - Ability to read and interpret PCB schematics and understand SoC internal blocks (CPUs, Interconnects, Memory) - A 'safety-first' mindset, extreme attention to detail, and the ability to explain complex failure modes to design engineers Preferred Qualifications: - Experience with safety analysis tools (e.g., Ansys medini analyze, Item Toolkit, or Reliability Workbench) - Knowledge of ASIL (Automotive Safety Integrity Level) decomposition strategies - Familiarity with hardware description languages (Verilog/VHDL) or hardware verification - Practical experience with physical layout constraints that impact DFA (e.g., substrate isolation, power domain separation) Required Skills: ISO 26262, Fault Tree Analysis (FTA), Dependent Failure Analysis (DFA), PCB schematic interpretation, System on Chip (SoC) architecture, Safety analysis tools, Automotive Safety Integrity Level (ASIL), Hardware description languages, Hardware verification, Physical layout constraints, Safety-first mindset, explain complex failure modes Benefits: Paid vacation, Paid sick leave, Medical insurance benefits