IP RTL Design Engineer

IP RTL Design Engineer Location: Bangalore About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. We are seeking a highly motivated RTL Design Engineer to architect and deliver next generation UCIe and high speed mixed signal IP. This role spans micro architecture definition through production quality RTL, with opportunities to act as both a strong individual contributor and a technical lead. What You Can Expect Responsibilities Architect, design, and implement state‑of‑the‑art RTL for UCIe and other high‑speed interface IP. Own micro‑architecture and RTL development for medium to high‑complexity digital blocks. Drive hands‑on execution including RTL coding, synthesis, CDC/RDC analysis, linting, debugging, and support for test and bring‑up. Partner closely with Architecture and Verification teams to define test plans, coverage strategies, and achieve verification closure. Participate in design reviews and contribute to IP quality, robustness, and reusability. Provide technical leadership by mentoring junior engineers, reviewing designs, and helping build a high‑performance design team. What We're Looking For Education & Experience BSEE/MSEE (or equivalent) in Electrical Engineering or related field. 8–14 years of hands‑on digital design experience delivering silicon‑proven IPs or SoCs. Technical Skills Strong domain expertise in high‑speed protocols such as UCIe, Ethernet, DDR, PCIe, USB (direct UCIe experience strongly preferred). Extensive hands‑on experience with SystemVerilog/Verilog (VHDL a plus). Proven experience with RTL quality and sign‑off flows including Lint, CDC/RDC (e.g., SpyGlass or equivalent). Solid understanding of synthesis, STA, formal checking, and downstream P&R interactions. Good grasp of SoC architecture, including processor cores, memories, interconnects, and peripheral interfaces. Behavioral & Leadership Skills Demonstrated ability to deliver production‑quality designs on aggressive schedules. Strong debugging, problem‑solving, and cross‑functional collaboration skills. Ability to take ownership, influence technical direction, and mentor less‑experienced engineers. Nice to Have Experience with low‑power design techniques and clocking architectures. Exposure to post‑silicon debug and silicon bring‑up. Prior experience delivering reusable IPs across multiple products or nodes. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1