IP DFT Engineer

Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality. Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks. Insert and connect MBIST logic, including test collars around memories, MBIST controllers, and electronic fuse (eFuse) logic, to core and Test Access Port (TAP) interfaces. Design Verification of DFT logic and test pattern generation. Develop DFT timing constraints in Synopsys Design Constraints (SDC) for DFT logic.