RTL Intern - Spring 2027

Summary: Etched is building the world’s first AI inference system purpose-built for transformers, offering unprecedented performance and cost efficiency. As an RTL Intern, you will design microarchitecture and implement logic in Verilog, contributing to RTL block development and participating in the full design cycle. Responsibilities: - Help design microarchitecture and implement logic in verilog - Work with cutting-edge machine learning architectures - Contribute to RTL block development - Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback Required Qualifications: - Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field - Familiarity with high-speed digital logic - Exposure to ASIC or SoC design concepts - Familiarity with SystemVerilog, UVM, or Python - Familiarity with verification work and writing test benches - Familiarity with physical design flows and tooling - Are able to learn quickly about transformers and other aspects of modern artificial intelligence Preferred Qualifications: - Familiarity with transformer models and machine learning - Familiarity with numerical representations and functions - Familiarity with clocking and reset schemes - Ability to program with Python or another scripting language Required Skills: Verilog, Microarchitecture design, High-speed digital logic, ASIC design concepts, SoC design concepts, SystemVerilog, UVM, Python, Verification and test bench writing, Physical design flows and tooling Internship Start Date: Start in 2027 Spring Benefits: Generous housing support for those relocating, Daily lunch and dinner in our office, Direct mentorship from industry leaders and world-class engineers