Etched→
DFT Intern - Fall 2026
InternshipOn-siteFull-time
Location
San Jose, CA
Salary
Not listed
Experience
No experience required
Posted
Today
Skills
verilogsystemverilogasic designsoc designdigital logic designasic design flowstatic timing analysisdesign for test (dft)pythontclmbistscan insertionscan compressiontessentatpg fault modelsclocking schemesreset schemes
Job Description
Summary: Etched is building the world’s first AI inference system purpose-built for transformers, delivering over 10x higher performance and dramatically lower cost and latency. As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression and work across design teams, contributing to DFT verification and developing flows for various ATPG fault models.
Responsibilities:
- Help review and refine DFT flow automation to support chip-level regression on Caelius
- Work across frontend and backend design teams
- Contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations)
- Develop flows for various ATPG fault models
Required Qualifications:
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field
- Familiarity with a hardware description language (Verilog or SystemVerilog)
- Exposure to ASIC or SoC design concepts
- Familiarity with digital logic design fundamentals
- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
- Familiarity with scripting in Python, Tcl, or another language
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Preferred Qualifications:
- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
- Experience with Tessent or similar DFT tooling
- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
- Exposure to DFT flow automation or regression infrastructure
- Familiarity with clocking and reset schemes
Required Skills: Verilog, SystemVerilog, ASIC design, SoC design, Digital logic design, ASIC design flow, Static timing analysis, Design for test (DFT), Python, Tcl, MBIST, Scan insertion, Scan compression, Tessent, ATPG fault models, Clocking schemes, Reset schemes
Internship Start Date: Start in 2026 Fall
Benefits: Generous housing support for those relocating, Daily lunch and dinner in our office, Direct mentorship from industry leaders and world-class engineers
Benefits
Generous housing support for those relocating
Daily lunch and dinner in our office
Direct mentorship from industry leaders and world-class engineers