Back to TsentaBaud LabsFounding ASIC Architect / RTL & FPGA LeadEntry LevelOn-siteLocationNew York City, NYSalary$160k–$250k/yrExperienceNot specifiedPostedTodayInterested in this role?Auto apply with Tsenta. AI tailors your resume and fills out the application for you.Apply with TsentaRelevant MajorsSemiconductor / Chip Design, Electrical / Hardware Engineer